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DDR Interface 16/32-bit at 400 MHz data rate
512 Kbytes
M2
Memory
CLASS
10 Mbytes
M3
Memory
128-bit at
400 MHz
DDR
Controller
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
QUICC Engine
Subsystem
Serial RapidIO
Semaphores
Four DSP
Subsystems
128 Kbyte
L2
ICache
Dual RISC
Processors
Subsystem
RMU SRIO
Virtual
Interrupts
Boot ROM
Ethernet
Ethernet
ATM
SPI
I 2 C
JTAG
Other
Modules
Eight TDMs
256-Channels each
10/100/1000 Mbps
10/100/1000 Mbps
SPI
16-bit/8-bit
1x/4x
PCI 32-bit
33/66 MHz
Note: The arrow direction indicates master or slave.
UTOPIA
Figure 1. MSC8144 Block Diagram
Two Internal Buses
(128 bits wide each)
Interrupts
Bus Interface
IQBus
DQBus
EPIC
Timer
TWB
Task
Protection
Debug Support
OCE30 DPU
Instruction
Cache
Write-
Through
Buffer
(WTB)
Data
Cache
Write-
Back
Buffer
(WBB)
Address
Translation
MMU
P-bus
SC3400
Core
Xa-bus
Xb-bus
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
3
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